A memory management unit (MMU) is configured to perform address translation (and other memory management functions) for processors or peripheral devices (generally referred to as an upstream client or device). For example, an MMU may comprise a translation lookaside buffer (TLB) as known in the art to perform virtual to physical memory address translations.
With reference to FIG. 1, a conventional MMU 104 receives a client input transaction 116 (e.g., a request to read or write an address) from upstream client device 102 and if a translation exists in MMU 104 for client input transaction 116, MMU 104 performs address translation. The address translation information is used to translate the address in the client input transaction request 116 to an address for client output transaction 120.
MMU 104 is shown in more detail in FIG. 1. MMU 104 can include translation cache 108 which stores results of previously completed (or partially completed) translations. Client input transactions 116 that cannot be translated using information stored in translation cache 108 are resolved by performing a process called a “translation table walk” using translation table walker (TTW) 114. A particular entry (shown as TTW0 112) corresponding to the particular client input transaction 116 is used to perform translation table walks for the translation request. In some cases, translation table walk requests can be sent from bus 124, through bus 120 to system memory 106, wherein, response 122 can include corresponding translation information received from system memory 106 (a downstream device) and used to populate translation cache 108. In some cases, client output transactions can be sent on bus 120, wherein, response 122 can pertain to the client output transactions and be sent to upstream client device 102.
As numerous client input transactions 116 may be received before they can be serviced in the above manner, client input transactions 116 are placed in transaction queue 110 before they can access translation cache 108. Client input transactions 116 at the head of transaction queue 110 are serially allowed to access translation cache 108. If no translation is found in translation cache 108 for client input transaction 116 at the head of transaction queue 110, all other transactions in transaction queue 110 are forced to wait until a translation result for client input transaction 116 at the head of transaction queue 110 is obtained from the translation table walk process using TTW 114 and access of system memory 106. During the time that the translation for client input transaction 116 at the head of transaction queue 110 is obtained, MMU 104 is stalled, and therefore performance of MMU 104 degrades.
Accordingly, there is a need in the art to overcome the aforementioned drawbacks of conventional MMUs comprising a single translation table walker (e.g., TTW 114) capable of only servicing one translation table walk at a time and a transaction queue (e.g., transaction queue 110) capable of processing only one transaction at a time.